Phaselock loop circuits (PLL's) have routinely been used as part of conventional control circuitry with a wide range of applications, mainly in the field of communications. Circuits of this type have advantageously been implemented with analog components as the most effective way of providing the necessary functions. More recently though, PLL's have also been successfully implemented using digital circuitry.
The principles and applications of PLL's have been known for many years and referred to in a variety of patents and publications, some of which are listed below.
A detailed description of design techniques and operation of PLL's are described in a textbook by F. M. Gardner, "Phaselock Techniques", published by John Wiley & Sons, 1976.
A phase shifter VCO which includes amplifiers and difference amplifiers is described in U.S. Pat. No. 4,799,028 to Weaver et al, in which both the timing element and phase shifter oscillator are implemented with analog components.
A VCO used as integral part of an analog PLL has been described in U.S. Pat. No. 4,942,370 to Toshihiro Shigemori, whereby a PLL circuit is shown comprising a phase comparator for inputting input and output clock signals, for detecting differences in phase between both of these signals, and for outputting a signal based on the phase difference. These and other functions are provided by a phase comparator driving a proportional circuit and an integral circuit feeding the VCO.
Further representations of a VCO used jointly with an analog PLL is described in U.S. Pat. No. 4,920,322 to Jan B. F. W. Ruijs, in which a VCO is used in a phaselock loop which includes a phase detector for generating an error signal representative of a phase difference between a reference signal and a signal taken from the VCO, and a loop filter for producing a control signal from the error signal.
A further analog representation of a VCO used jointly with a PLL is described in U.S. Pat. No. 4,908,582 to Mitsumo Kawano, et al., in which an automatic frequency control circuit uses counters, flip flops and logic gates to control a VCO but leaves the VCO and adjoining PLL functionally in analog form. The same is also true for the Interruptible VCO and PLL described in U.S. Pat. No. 4,565,976 to David L. Campbell which are of the analog type, thereby using continuously variable voltage signals for controlling the frequency of the VCO.
In U.S. Pat. No. 4,570,130 to David R. Grindel, et al and of common assignee, an analog PLL oscillator is provided with a VCO which includes a current controlled oscillator and an input controller therefor that maintains the center frequency of the current controlled oscillator substantially constant regardless of changes in the gain of the VCO. Grindel provides a VCO with improved center of frequency vs control voltage characteristics using appropriate analog functions implemented with analog components.
It has been found that with the ever increasing number of transistors available in monolithic integrated circuits, a trend has developed towards replacing analog functions with digital elements. This process has mainly been driven by cost reductions inherent in monolithic implementations. Complicating this process has been a desire of the device designer to optimize the device/process for digital IC performance. This optimization is frequently at odds with implementing precision analog functions using the same technology.
None of the above references attempt to solve a distinct problem germane to monolithic integrated circuits, whereby precise control of processing parameters is not possible nor feasible, leading to aberrations in the operation of a PLL and VCO associated with it.
It is known, particularly in communication applications, that it is desirable to correlate the frequency of a clock to a frequency many times that of an input reference clock. Since it is presently not feasible to guarantee that a monolithic oscillator will generate an exact frequency due to process and environmental variations, a precise control mechanism is required to adjust the frequency and phase.
A common technique to achieve phase and frequency control of an oscillator is to embed a controllable oscillator in a PLL which forces it to track the frequency and phase of the input reference. To perform a frequency multiplication as desired, the output of an on-chip oscillator must be divided by a predetermined factor, e.g., 10 in frequency. It is this reduced frequency which can be used by the PLL to lock the reference input.
To further understand the operation of a PLL and the control of certain key parameters, the following definitions are required:
A Lock-in Range refers to how close an input frequency must be to the VCO free-running frequency before the feedback loop (or loop, in short) acquires phase lock with no cycle slips.
A Pull-in Range is defined as the frequency range over which the loop will follow changes in the input frequency. More specifically, it refers to how far the input frequency can deviate from the VCO free running frequency.
A simple first-order loop is characterized by a single parameter called the loop gain K, which determines the lock-in and pull-in ranges, in accordance with the following relationship: EQU 2.pi.lock-in range2=.pi.pull-in range =K.
A more precise control of the lock-in capability of a PLL can be achieved by incorporating a Sequential Phase Error Detector (SPED) circuit in the feedback loop of the PLL. The SPED circuit greatly facilitates the design of a PLL by allowing it to "pull-in" over a wider range of frequencies. It also compensates for deviations that normally occur in the free running frequency of the VCO due to process variations, while simultaneously providing low-jitter operation which is essential for low error rates.